# git rev-parse -q --verify fedb8da96355f5f64353625bf96dc69423ad1826^{commit} fedb8da96355f5f64353625bf96dc69423ad1826 already have revision, skipping fetch # git checkout -q -f -B kisskb fedb8da96355f5f64353625bf96dc69423ad1826 # git clean -qxdf # < git log -1 # commit fedb8da96355f5f64353625bf96dc69423ad1826 # Author: John David Anglin # Date: Sun Aug 5 13:30:31 2018 -0400 # # parisc: Define mb() and add memory barriers to assembler unlock sequences # # For years I thought all parisc machines executed loads and stores in # order. However, Jeff Law recently indicated on gcc-patches that this is # not correct. There are various degrees of out-of-order execution all the # way back to the PA7xxx processor series (hit-under-miss). The PA8xxx # series has full out-of-order execution for both integer operations, and # loads and stores. # # This is described in the following article: # http://web.archive.org/web/20040214092531/http://www.cpus.hp.com/technical_references/advperf.shtml # # For this reason, we need to define mb() and to insert a memory barrier # before the store unlocking spinlocks. This ensures that all memory # accesses are complete prior to unlocking. The ldcw instruction performs # the same function on entry. # # Signed-off-by: John David Anglin # Cc: stable@vger.kernel.org # 4.0+ # Signed-off-by: Helge Deller # < /opt/cross/kisskb/br-microblaze-full-2016.08-613-ge98b4dd/bin/microblazeel-linux-gcc --version # < git log --format=%s --max-count=1 fedb8da96355f5f64353625bf96dc69423ad1826 # < make -s -j 80 ARCH=microblaze O=/kisskb/build/linus_mmu_defconfig_microblaze CROSS_COMPILE=/opt/cross/kisskb/br-microblaze-full-2016.08-613-ge98b4dd/bin/microblazeel-linux- mmu_defconfig # make -s -j 80 ARCH=microblaze O=/kisskb/build/linus_mmu_defconfig_microblaze CROSS_COMPILE=/opt/cross/kisskb/br-microblaze-full-2016.08-613-ge98b4dd/bin/microblazeel-linux- Kernel: arch/microblaze/boot/linux.bin is ready (#1) Completed OK # rm -rf /kisskb/build/linus_mmu_defconfig_microblaze # Build took: 0:00:47.034349