Buildresult: linus/pseries_le_defconfig/powerpc-gcc5 built on Aug 15 2018, 04:09

kisskb

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Status:	OK
Date/Time:	Aug 15 2018, 04:09
Duration:	0:02:22.959901
Builder:	ka1
Revision:	Merge branch 'l1tf-final' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip (`958f338e96f874a0d29442396d6adf9c1e17aa2d)`
Target:	linus/pseries_le_defconfig/powerpc-gcc5
Branch:	linus
Compiler:	powerpc-gcc5 (powerpc64le-linux-gcc (GCC) 5.2.0)
Config:	pseries_le_defconfig (download)
Log:	Download original Possible warnings (1) WARNING: modpost: Found 3 section mismatch(es). Full Log # git rev-parse -q --verify 958f338e96f874a0d29442396d6adf9c1e17aa2d^{commit} 958f338e96f874a0d29442396d6adf9c1e17aa2d already have revision, skipping fetch # git checkout -q -f -B kisskb 958f338e96f874a0d29442396d6adf9c1e17aa2d # git clean -qxdf # < git log -1 # commit 958f338e96f874a0d29442396d6adf9c1e17aa2d # Merge: 781fca5 07d981a # Author: Linus Torvalds <torvalds@linux-foundation.org> # Date: Tue Aug 14 09:46:06 2018 -0700 # # Merge branch 'l1tf-final' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip # # Merge L1 Terminal Fault fixes from Thomas Gleixner: # "L1TF, aka L1 Terminal Fault, is yet another speculative hardware # engineering trainwreck. It's a hardware vulnerability which allows # unprivileged speculative access to data which is available in the # Level 1 Data Cache when the page table entry controlling the virtual # address, which is used for the access, has the Present bit cleared or # other reserved bits set. # # If an instruction accesses a virtual address for which the relevant # page table entry (PTE) has the Present bit cleared or other reserved # bits set, then speculative execution ignores the invalid PTE and loads # the referenced data if it is present in the Level 1 Data Cache, as if # the page referenced by the address bits in the PTE was still present # and accessible. # # While this is a purely speculative mechanism and the instruction will # raise a page fault when it is retired eventually, the pure act of # loading the data and making it available to other speculative # instructions opens up the opportunity for side channel attacks to # unprivileged malicious code, similar to the Meltdown attack. # # While Meltdown breaks the user space to kernel space protection, L1TF # allows to attack any physical memory address in the system and the # attack works across all protection domains. It allows an attack of SGX # and also works from inside virtual machines because the speculation # bypasses the extended page table (EPT) protection mechanism. # # The assoicated CVEs are: CVE-2018-3615, CVE-2018-3620, CVE-2018-3646 # # The mitigations provided by this pull request include: # # - Host side protection by inverting the upper address bits of a non # present page table entry so the entry points to uncacheable memory. # # - Hypervisor protection by flushing L1 Data Cache on VMENTER. # # - SMT (HyperThreading) control knobs, which allow to 'turn off' SMT # by offlining the sibling CPU threads. The knobs are available on # the kernel command line and at runtime via sysfs # # - Control knobs for the hypervisor mitigation, related to L1D flush # and SMT control. The knobs are available on the kernel command line # and at runtime via sysfs # # - Extensive documentation about L1TF including various degrees of # mitigations. # # Thanks to all people who have contributed to this in various ways - # patches, review, testing, backporting - and the fruitful, sometimes # heated, but at the end constructive discussions. # # There is work in progress to provide other forms of mitigations, which # might be less horrible performance wise for a particular kind of # workloads, but this is not yet ready for consumption due to their # complexity and limitations" # # * 'l1tf-final' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (75 commits) # x86/microcode: Allow late microcode loading with SMT disabled # tools headers: Synchronise x86 cpufeatures.h for L1TF additions # x86/mm/kmmio: Make the tracer robust against L1TF # x86/mm/pat: Make set_memory_np() L1TF safe # x86/speculation/l1tf: Make pmd/pud_mknotpresent() invert # x86/speculation/l1tf: Invert all not present mappings # cpu/hotplug: Fix SMT supported evaluation # KVM: VMX: Tell the nested hypervisor to skip L1D flush on vmentry # x86/speculation: Use ARCH_CAPABILITIES to skip L1D flush on vmentry # x86/speculation: Simplify sysfs report of VMX L1TF vulnerability # Documentation/l1tf: Remove Yonah processors from not vulnerable list # x86/KVM/VMX: Don't set l1tf_flush_l1d from vmx_handle_external_intr() # x86/irq: Let interrupt handlers set kvm_cpu_l1tf_flush_l1d # x86: Don't include linux/irq.h from asm/hardirq.h # x86/KVM/VMX: Introduce per-host-cpu analogue of l1tf_flush_l1d # x86/irq: Demote irq_cpustat_t::__softirq_pending to u16 # x86/KVM/VMX: Move the l1tf_flush_l1d test to vmx_l1d_flush() # x86/KVM/VMX: Replace 'vmx_l1d_flush_always' with 'vmx_l1d_flush_cond' # x86/KVM/VMX: Don't set l1tf_flush_l1d to true from vmx_l1d_flush() # cpu/hotplug: detect SMT disabled by BIOS # ... # < /opt/cross/kisskb/gcc-5.2.0-nolibc/powerpc64le-linux/bin/powerpc64le-linux-gcc --version # < git log --format=%s --max-count=1 958f338e96f874a0d29442396d6adf9c1e17aa2d # < make -s -j 48 ARCH=powerpc O=/kisskb/build/linus_pseries_le_defconfig_ppc64le CROSS_COMPILE=/opt/cross/kisskb/gcc-5.2.0-nolibc/powerpc64le-linux/bin/powerpc64le-linux- pseries_le_defconfig # make -s -j 48 ARCH=powerpc O=/kisskb/build/linus_pseries_le_defconfig_ppc64le CROSS_COMPILE=/opt/cross/kisskb/gcc-5.2.0-nolibc/powerpc64le-linux/bin/powerpc64le-linux- WARNING: modpost: Found 3 section mismatch(es). To see full details build your kernel with: 'make CONFIG_DEBUG_SECTION_MISMATCH=y' Completed OK # rm -rf /kisskb/build/linus_pseries_le_defconfig_ppc64le # Build took: 0:02:22.959901

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