# git rev-parse -q --verify 0570bc8b7c9b41deba6f61ac218922e7168ad648^{commit} 0570bc8b7c9b41deba6f61ac218922e7168ad648 already have revision, skipping fetch # git checkout -q -f -B kisskb 0570bc8b7c9b41deba6f61ac218922e7168ad648 # git clean -qxdf # < git log -1 # commit 0570bc8b7c9b41deba6f61ac218922e7168ad648 # Merge: 0e2a5b5bd9a6 2d69fbf3d01a # Author: Linus Torvalds # Date: Thu Jul 18 12:26:59 2019 -0700 # # Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux # # Pull RISC-V updates from Paul Walmsley: # # - Hugepage support # # - "Image" header support for RISC-V kernel binaries, compatible with # the current ARM64 "Image" header # # - Initial page table setup now split into two stages # # - CONFIG_SOC support (starting with SiFive SoCs) # # - Avoid reserving memory between RAM start and the kernel in # setup_bootmem() # # - Enable high-res timers and dynamic tick in the RV64 defconfig # # - Remove long-deprecated gate area stubs # # - MAINTAINERS updates to switch to the newly-created shared RISC-V git # tree, and to fix a get_maintainers.pl issue for patches involving # SiFive E-mail addresses # # Also, one integration fix to resolve a build problem introduced during # in the v5.3-rc1 merge window: # # - Fix build break after macro-to-function conversion in # asm-generic/cacheflush.h # # * tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: # riscv: fix build break after macro-to-function conversion in generic cacheflush.h # RISC-V: Add an Image header that boot loader can parse. # RISC-V: Setup initial page tables in two stages # riscv: remove free_initrd_mem # riscv: ccache: Remove unused variable # riscv: Introduce huge page support for 32/64bit kernel # x86, arm64: Move ARCH_WANT_HUGE_PMD_SHARE config in arch/Kconfig # RISC-V: Fix memory reservation in setup_bootmem() # riscv: defconfig: enable SOC_SIFIVE # riscv: select SiFive platform drivers with SOC_SIFIVE # arch: riscv: add config option for building SiFive's SoC resource # riscv: Remove gate area stubs # MAINTAINERS: change the arch/riscv git tree to the new shared tree # MAINTAINERS: don't automatically patches involving SiFive to the linux-riscv list # RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERS # < /opt/cross/kisskb/gcc-4.6.3-nolibc/mips-linux/bin/mips-linux-gcc --version # < /opt/cross/kisskb/gcc-4.6.3-nolibc/mips-linux/bin/mips-linux-ld --version # < git log --format=%s --max-count=1 0570bc8b7c9b41deba6f61ac218922e7168ad648 # < make -s -j 48 ARCH=mips O=/kisskb/build/linus_mips-allnoconfig_mips CROSS_COMPILE=/opt/cross/kisskb/gcc-4.6.3-nolibc/mips-linux/bin/mips-linux- allnoconfig # make -s -j 48 ARCH=mips O=/kisskb/build/linus_mips-allnoconfig_mips CROSS_COMPILE=/opt/cross/kisskb/gcc-4.6.3-nolibc/mips-linux/bin/mips-linux- :1511:2: warning: #warning syscall clone3 not implemented [-Wcpp] /kisskb/src/arch/mips/vdso/Makefile:39: MIPS VDSO requires binutils >= 2.25 /kisskb/src/kernel/printk/printk.c: In function 'devkmsg_sysctl_set_loglvl': /kisskb/src/kernel/printk/printk.c:194:16: warning: 'old' may be used uninitialized in this function [-Wuninitialized] FIT description: Linux 5.2.0+ Created: Fri Jul 19 07:26:26 2019 Image 0 (kernel@0) Description: Linux 5.2.0+ Created: Fri Jul 19 07:26:26 2019 Type: Kernel Image Compression: gzip compressed Data Size: 642908 Bytes = 627.84 KiB = 0.61 MiB Architecture: MIPS OS: Linux Load Address: 0x80100000 Entry Point: 0x8021f0c0 Hash algo: sha1 Hash value: afd0feae57055b2eedccefb2ffeaf6cd45de166d Default Configuration: 'conf@default' Configuration 0 (conf@default) Description: Generic Linux kernel Kernel: kernel@0 Completed OK # rm -rf /kisskb/build/linus_mips-allnoconfig_mips # Build took: 0:00:13.300758