# git rev-parse -q --verify 0570bc8b7c9b41deba6f61ac218922e7168ad648^{commit} 0570bc8b7c9b41deba6f61ac218922e7168ad648 already have revision, skipping fetch # git checkout -q -f -B kisskb 0570bc8b7c9b41deba6f61ac218922e7168ad648 # git clean -qxdf # < git log -1 # commit 0570bc8b7c9b41deba6f61ac218922e7168ad648 # Merge: 0e2a5b5bd9a6 2d69fbf3d01a # Author: Linus Torvalds # Date: Thu Jul 18 12:26:59 2019 -0700 # # Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux # # Pull RISC-V updates from Paul Walmsley: # # - Hugepage support # # - "Image" header support for RISC-V kernel binaries, compatible with # the current ARM64 "Image" header # # - Initial page table setup now split into two stages # # - CONFIG_SOC support (starting with SiFive SoCs) # # - Avoid reserving memory between RAM start and the kernel in # setup_bootmem() # # - Enable high-res timers and dynamic tick in the RV64 defconfig # # - Remove long-deprecated gate area stubs # # - MAINTAINERS updates to switch to the newly-created shared RISC-V git # tree, and to fix a get_maintainers.pl issue for patches involving # SiFive E-mail addresses # # Also, one integration fix to resolve a build problem introduced during # in the v5.3-rc1 merge window: # # - Fix build break after macro-to-function conversion in # asm-generic/cacheflush.h # # * tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: # riscv: fix build break after macro-to-function conversion in generic cacheflush.h # RISC-V: Add an Image header that boot loader can parse. # RISC-V: Setup initial page tables in two stages # riscv: remove free_initrd_mem # riscv: ccache: Remove unused variable # riscv: Introduce huge page support for 32/64bit kernel # x86, arm64: Move ARCH_WANT_HUGE_PMD_SHARE config in arch/Kconfig # RISC-V: Fix memory reservation in setup_bootmem() # riscv: defconfig: enable SOC_SIFIVE # riscv: select SiFive platform drivers with SOC_SIFIVE # arch: riscv: add config option for building SiFive's SoC resource # riscv: Remove gate area stubs # MAINTAINERS: change the arch/riscv git tree to the new shared tree # MAINTAINERS: don't automatically patches involving SiFive to the linux-riscv list # RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERS # < /opt/cross/kisskb/fe-x86-64-core-i7-2017.05/bin/x86_64-linux-gcc --version # < /opt/cross/kisskb/fe-x86-64-core-i7-2017.05/bin/x86_64-linux-ld --version # < git log --format=%s --max-count=1 0570bc8b7c9b41deba6f61ac218922e7168ad648 # < make -s -j 48 ARCH=x86_64 O=/kisskb/build/linus-rand_x86_64-randconfig_um-x86_64 CROSS_COMPILE=/opt/cross/kisskb/fe-x86-64-core-i7-2017.05/bin/x86_64-linux- randconfig KCONFIG_SEED=0xEDA9A4E4 # Added to kconfig CONFIG_STANDALONE=y # Added to kconfig CONFIG_PREVENT_FIRMWARE_BUILD=y # Added to kconfig CONFIG_CC_STACKPROTECTOR_STRONG=n # Added to kconfig CONFIG_GCC_PLUGINS=n # Added to kconfig CONFIG_GCC_PLUGIN_CYC_COMPLEXITY=n # Added to kconfig CONFIG_GCC_PLUGIN_SANCOV=n # Added to kconfig CONFIG_GCC_PLUGIN_LATENT_ENTROPY=n # yes \n | make -s -j 48 ARCH=x86_64 O=/kisskb/build/linus-rand_x86_64-randconfig_um-x86_64 CROSS_COMPILE=/opt/cross/kisskb/fe-x86-64-core-i7-2017.05/bin/x86_64-linux- oldconfig yes: standard output: Broken pipe # make -s -j 48 ARCH=x86_64 O=/kisskb/build/linus-rand_x86_64-randconfig_um-x86_64 CROSS_COMPILE=/opt/cross/kisskb/fe-x86-64-core-i7-2017.05/bin/x86_64-linux- You are building kernel with non-retpoline compiler. Please update your compiler. make[1]: *** [arch/x86/Makefile:308: checkbin] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:179: sub-make] Error 2 Command 'make -s -j 48 ARCH=x86_64 O=/kisskb/build/linus-rand_x86_64-randconfig_um-x86_64 CROSS_COMPILE=/opt/cross/kisskb/fe-x86-64-core-i7-2017.05/bin/x86_64-linux- ' returned non-zero exit status 2 # rm -rf /kisskb/build/linus-rand_x86_64-randconfig_um-x86_64 # Build took: 0:00:05.771779