# git rev-parse -q --verify 7ddb58cb0ecae8e8b6181d736a87667cc9ab8389^{commit}
7ddb58cb0ecae8e8b6181d736a87667cc9ab8389
already have revision, skipping fetch
# git checkout -q -f -B kisskb 7ddb58cb0ecae8e8b6181d736a87667cc9ab8389
# git clean -qxdf
# < git log -1
# commit 7ddb58cb0ecae8e8b6181d736a87667cc9ab8389
# Merge: ce840177930f e2ceaa867d26
# Author: Linus Torvalds <torvalds@linux-foundation.org>
# Date:   Wed Nov 3 21:18:44 2021 -0700
# 
#     Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
#     
#     Pull clk updates from Stephen Boyd:
#      "The usual collection of clk driver updates and new driver additions.
#       In terms of lines it's mainly Qualcomm and Mediatek code, supporting
#       various SoCs and their multitude of clk controllers.
#     
#       New Drivers:
#        - GCC and RPMcc support for Qualcomm QCM2290 SoCs
#        - GCC support for Qualcomm MSM8994/MSM8992 SoCs
#        - LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
#        - Support for Mediatek MT8195 SoCs
#        - Initial clock driver for the Exynos850 SoC
#        - Add i.MX8ULP clock driver and related bindings
#     
#       Updates:
#        - Clock power management for new SAMA7G5 SoC
#        - Updates to the master clock driver and sam9x60-pll to be able to
#          use cpufreq-dt driver and avoid overclocking of CPU and MCK0
#          domains while changing the frequency via DVFS
#        - Use ARRAY_SIZE in qcom clk drivers
#        - Remove some impractical fallback parent names in qcom clk drivers
#        - Make Mediatek clk drivers tristate
#        - Refactoring of the CPU clock code and conversion of Samsung
#          Exynos5433 CPU clock driver to the platform driver
#        - A few conversions to devm_platform_ioremap_resource()
#        - Updates of the Samsung Kconfig help text
#        - Update video path realted clocks for Amlogic meson8
#        - Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L
#        - Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U
#        - Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N
#        - Remove unused helpers from i.MX specific clock header
#        - Rework all i.MX clk based helpers to use clk_hw based ones
#        - Rework i.MX gate/mux/divider wrappers
#        - Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers
#        - Update i.MX pllv4 and composite clocks to support i.MX8ULP
#        - Disable i.MX7ULP composite clock during initialization
#        - Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite
#        - Disable the i.MX pfd when set pfdv2 clock rate
#        - Add support for i.MX8ULP in pfdv2
#        - Add the pcc reset controller support on i.MX8ULP
#        - Fix the build break when clk-imx8ulp is built as module
#        - Move csi_sel mux to correct base register in i.MX6UL clock drivr
#        - Fix csi clk gate register in i.MX6UL clock driver
#        - Fix build bug making CLK_IMX8ULP select MXC_CLK
#        - Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U
#        - Add Ethernet clocks on Renesas RZ/G2L
#        - Move Rockchip to use module_platform_probe
#        - Enable usage of Coresight related clocks on Rockchip rk3399"
#     
#     * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (170 commits)
#       clk: use clk_core_get_rate_recalc() in clk_rate_get()
#       clk: at91: sama7g5: set low limit for mck0 at 32KHz
#       clk: at91: sama7g5: remove prescaler part of master clock
#       clk: at91: clk-master: add notifier for divider
#       clk: at91: clk-sam9x60-pll: add notifier for div part of PLL
#       clk: at91: clk-master: fix prescaler logic
#       clk: at91: clk-master: mask mckr against layout->mask
#       clk: at91: clk-master: check if div or pres is zero
#       clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL
#       clk: at91: pmc: add sama7g5 to the list of available pmcs
#       clk: at91: clk-master: improve readability by using local variables
#       clk: at91: clk-master: add register definition for sama7g5's master clock
#       clk: at91: sama7g5: add securam's peripheral clock
#       clk: at91: pmc: execute suspend/resume only for backup mode
#       clk: at91: re-factor clocks suspend/resume
#       clk: ux500: Add driver for the reset portions of PRCC
#       dt-bindings: clock: u8500: Rewrite in YAML and extend
#       clk: composite: Use rate_ops.determine_rate when also a mux is available
#       clk: samsung: describe drivers in Kconfig
#       clk: samsung: exynos5433: update apollo and atlas clock probing
#       ...
# < /opt/cross/kisskb/korg/gcc-5.5.0-nolibc/powerpc64-linux/bin/powerpc64-linux-gcc --version
# < /opt/cross/kisskb/korg/gcc-5.5.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld --version
# < git log --format=%s --max-count=1 7ddb58cb0ecae8e8b6181d736a87667cc9ab8389
# < make -s -j 32 ARCH=powerpc O=/kisskb/build/linus_pseries_le_defconfig_powerpc-gcc5 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-5.5.0-nolibc/powerpc64-linux/bin/powerpc64-linux-  pseries_le_defconfig
# < make -s -j 32 ARCH=powerpc O=/kisskb/build/linus_pseries_le_defconfig_powerpc-gcc5 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-5.5.0-nolibc/powerpc64-linux/bin/powerpc64-linux-  help
# make -s -j 32 ARCH=powerpc O=/kisskb/build/linus_pseries_le_defconfig_powerpc-gcc5 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-5.5.0-nolibc/powerpc64-linux/bin/powerpc64-linux-  olddefconfig
# make -s -j 32 ARCH=powerpc O=/kisskb/build/linus_pseries_le_defconfig_powerpc-gcc5 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-5.5.0-nolibc/powerpc64-linux/bin/powerpc64-linux-  
<stdin>:1559:2: warning: #warning syscall futex_waitv not implemented [-Wcpp]
Completed OK
# rm -rf /kisskb/build/linus_pseries_le_defconfig_powerpc-gcc5
# Build took: 0:03:39.991865