Buildresult: linus/rv32_defconfig/riscv-gcc11 built on Aug 2 2022, 07:50

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Status:	OK
Date/Time:	Aug 2 2022, 07:50
Duration:	0:00:50.972131
Builder:	ka4
Revision:	Merge tag 'irq-core-2022-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip (`9de1f9c8ca5100a02a2e271bdbde36202e251b4b)`
Target:	linus/rv32_defconfig/riscv-gcc11
Branch:	linus
Compiler:	riscv-gcc11 (riscv64-linux-gcc (GCC) 11.1.0 / GNU ld (GNU Binutils) 2.36.1)
Config:	rv32_defconfig (download)
Log:	Download original Possible warnings (1) .config:3865:warning: override: ARCH_RV32I changes choice state Full Log # git rev-parse -q --verify 9de1f9c8ca5100a02a2e271bdbde36202e251b4b^{commit} 9de1f9c8ca5100a02a2e271bdbde36202e251b4b already have revision, skipping fetch # git checkout -q -f -B kisskb 9de1f9c8ca5100a02a2e271bdbde36202e251b4b # git clean -qxdf # < git log -1 # commit 9de1f9c8ca5100a02a2e271bdbde36202e251b4b # Merge: dfea84827f7e 779fda86bdeb # Author: Linus Torvalds <torvalds@linux-foundation.org> # Date: Mon Aug 1 12:48:15 2022 -0700 # # Merge tag 'irq-core-2022-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip # # Pull irq updates from Thomas Gleixner: # "Updates for interrupt core and drivers: # # Core: # # - Fix a few inconsistencies between UP and SMP vs interrupt # affinities # # - Small updates and cleanups all over the place # # New drivers: # # - LoongArch interrupt controller # # - Renesas RZ/G2L interrupt controller # # Updates: # # - Hotpath optimization for SiFive PLIC # # - Workaround for broken PLIC edge triggered interrupts # # - Simall cleanups and improvements as usual" # # * tag 'irq-core-2022-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (52 commits) # irqchip/mmp: Declare init functions in common header file # irqchip/mips-gic: Check the return value of ioremap() in gic_of_init() # genirq: Use for_each_action_of_desc in actions_show() # irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch # irqchip: Add LoongArch CPU interrupt controller support # irqchip: Add Loongson Extended I/O interrupt controller support # irqchip/loongson-liointc: Add ACPI init support # irqchip/loongson-pch-msi: Add ACPI init support # irqchip/loongson-pch-pic: Add ACPI init support # irqchip: Add Loongson PCH LPC controller support # LoongArch: Prepare to support multiple pch-pic and pch-msi irqdomain # LoongArch: Use ACPI_GENERIC_GSI for gsi handling # genirq/generic_chip: Export irq_unmap_generic_chip # ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback # APCI: irq: Add support for multiple GSI domains # LoongArch: Provisionally add ACPICA data structures # irqdomain: Use hwirq_max instead of revmap_size for NOMAP domains # irqdomain: Report irq number for NOMAP domains # irqchip/gic-v3: Fix comment typo # dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/V2L SoC # ... # < /opt/cross/kisskb/korg/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux-gcc --version # < /opt/cross/kisskb/korg/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux-ld --version # < git log --format=%s --max-count=1 9de1f9c8ca5100a02a2e271bdbde36202e251b4b # < make -s -j 120 ARCH=riscv O=/kisskb/build/linus_rv32_defconfig_riscv-gcc11 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux- rv32_defconfig .config:3865:warning: override: ARCH_RV32I changes choice state # < make -s -j 120 ARCH=riscv O=/kisskb/build/linus_rv32_defconfig_riscv-gcc11 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux- help # make -s -j 120 ARCH=riscv O=/kisskb/build/linus_rv32_defconfig_riscv-gcc11 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux- olddefconfig # make -s -j 120 ARCH=riscv O=/kisskb/build/linus_rv32_defconfig_riscv-gcc11 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux- Completed OK # rm -rf /kisskb/build/linus_rv32_defconfig_riscv-gcc11 # Build took: 0:00:50.972131

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