# git rev-parse -q --verify 69dac8e431af26173ca0a1ebc87054e01c585bcc^{commit}
69dac8e431af26173ca0a1ebc87054e01c585bcc
already have revision, skipping fetch
# git checkout -q -f -B kisskb 69dac8e431af26173ca0a1ebc87054e01c585bcc
# git clean -qxdf
# < git log -1
# commit 69dac8e431af26173ca0a1ebc87054e01c585bcc
# Merge: 6c833c0581f1 5cef38dd03f3
# Author: Linus Torvalds <torvalds@linux-foundation.org>
# Date:   Fri Aug 12 18:39:43 2022 -0700
# 
#     Merge tag 'riscv-for-linus-5.20-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
#     
#     Pull more RISC-V updates from Palmer Dabbelt:
#      "There's still a handful of new features in here, but there are a lot
#       of fixes/cleanups as well:
#     
#        - Support for the Zicbom extension for explicit cache-block
#          management, along with the necessary bits to make the non-standard
#          cache management ops on the Allwinner D1 function
#     
#        - Support for the Zihintpause extension, which codifies a go-slow
#          instruction used for cpu_relax()
#     
#        - Support for the Sstc extension for supervisor-mode timer/counter
#          management
#     
#        - Many device tree fixes and cleanups, including a large set for the
#          Canaan device trees
#     
#        - A handful of fixes and cleanups for the PMU driver"
#     
#     * tag 'riscv-for-linus-5.20-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (43 commits)
#       dt-bindings: gpio: sifive: add gpio-line-names
#       wireguard: selftests: set CONFIG_NONPORTABLE on riscv32
#       RISC-V: KVM: Support sstc extension
#       RISC-V: Improve SBI definitions
#       RISC-V: Move counter info definition to sbi header file
#       RISC-V: Fix SBI PMU calls for RV32
#       RISC-V: Update user page mapping only once during start
#       RISC-V: Fix counter restart during overflow for RV32
#       RISC-V: Prefer sstc extension if available
#       RISC-V: Enable sstc extension parsing from DT
#       RISC-V: Add SSTC extension CSR details
#       riscv:uprobe fix SR_SPIE set/clear handling
#       dt-bindings: riscv: fix SiFive l2-cache's cache-sets
#       riscv: ensure cpu_ops_sbi is declared
#       RISC-V: cpu_ops_spinwait.c should include head.h
#       RISC-V: Declare cpu_ops_spinwait in <asm/cpu_ops.h>
#       riscv: dts: starfive: correct number of external interrupts
#       riscv: dts: sifive unmatched: Add PWM controlled LEDs
#       riscv/purgatory: Omit use of bin2c
#       riscv/purgatory: hard-code obj-y in Makefile
#       ...
# < /opt/cross/kisskb/korg/gcc-5.5.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc --version
# < /opt/cross/kisskb/korg/gcc-5.5.0-nolibc/aarch64-linux/bin/aarch64-linux-ld --version
# < git log --format=%s --max-count=1 69dac8e431af26173ca0a1ebc87054e01c585bcc
# < make -s -j 120 ARCH=arm64 O=/kisskb/build/kbuild_arm64-defconfig_arm64-gcc5 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-5.5.0-nolibc/aarch64-linux/bin/aarch64-linux-  defconfig
# < make -s -j 120 ARCH=arm64 O=/kisskb/build/kbuild_arm64-defconfig_arm64-gcc5 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-5.5.0-nolibc/aarch64-linux/bin/aarch64-linux-  help
# make -s -j 120 ARCH=arm64 O=/kisskb/build/kbuild_arm64-defconfig_arm64-gcc5 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-5.5.0-nolibc/aarch64-linux/bin/aarch64-linux-  olddefconfig
# make -s -j 120 ARCH=arm64 O=/kisskb/build/kbuild_arm64-defconfig_arm64-gcc5 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-5.5.0-nolibc/aarch64-linux/bin/aarch64-linux-  
Completed OK
# rm -rf /kisskb/build/kbuild_arm64-defconfig_arm64-gcc5
# Build took: 0:02:01.100238