Buildresult: linus/malta_defconfig/mips-gcc8 built on Feb 26 2023, 05:37

kisskb

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Status:	OK
Date/Time:	Feb 26 2023, 05:37
Duration:	0:02:12.000813
Builder:	alpine3
Revision:	Merge tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl (`7c3dc440b1f5c75f45e24430f913e561dc82a419)`
Target:	linus/malta_defconfig/mips-gcc8
Branch:	linus
Compiler:	mips-gcc8 (mips-linux-gcc (GCC) 8.5.0 / GNU ld (GNU Binutils) 2.36.1)
Config:	malta_defconfig (download)
Log:	Download original No warnings found in log. Full Log # git rev-parse -q --verify 7c3dc440b1f5c75f45e24430f913e561dc82a419^{commit} 7c3dc440b1f5c75f45e24430f913e561dc82a419 already have revision, skipping fetch # git checkout -q -f -B kisskb 7c3dc440b1f5c75f45e24430f913e561dc82a419 # git clean -qxdf # < git log -1 # commit 7c3dc440b1f5c75f45e24430f913e561dc82a419 # Merge: d8e473182ab9 e686c32590f4 # Author: Linus Torvalds <torvalds@linux-foundation.org> # Date: Sat Feb 25 09:19:23 2023 -0800 # # Merge tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl # # Pull Compute Express Link (CXL) updates from Dan Williams: # "To date Linux has been dependent on platform-firmware to map CXL RAM # regions and handle events / errors from devices. With this update we # can now parse / update the CXL memory layout, and report events / # errors from devices. This is a precursor for the CXL subsystem to # handle the end-to-end "RAS" flow for CXL memory. i.e. the flow that # for DDR-attached-DRAM is handled by the EDAC driver where it maps # system physical address events to a field-replaceable-unit (FRU / # endpoint device). In general, CXL has the potential to standardize # what has historically been a pile of memory-controller-specific error # handling logic. # # Another change of note is the default policy for handling RAM-backed # device-dax instances. Previously the default access mode was "device", # mmap(2) a device special file to access memory. The new default is # "kmem" where the address range is assigned to the core-mm via # add_memory_driver_managed(). This saves typical users from wondering # why their platform memory is not visible via free(1) and stuck behind # a device-file. At the same time it allows expert users to deploy # policy to, for example, get dedicated access to high performance # memory, or hide low performance memory from general purpose kernel # allocations. This affects not only CXL, but also systems with # high-bandwidth-memory that platform-firmware tags with the # EFI_MEMORY_SP (special purpose) designation. # # Summary: # # - CXL RAM region enumeration: instantiate 'struct cxl_region' objects # for platform firmware created memory regions # # - CXL RAM region provisioning: complement the existing PMEM region # creation support with RAM region support # # - "Soft Reservation" policy change: Online (memory hot-add) # soft-reserved memory (EFI_MEMORY_SP) by default, but still allow # for setting aside such memory for dedicated access via device-dax. # # - CXL Events and Interrupts: Takeover CXL event handling from # platform-firmware (ACPI calls this CXL Memory Error Reporting) and # export CXL Events via Linux Trace Events. # # - Convey CXL _OSC results to drivers: Similar to PCI, let the CXL # subsystem interrogate the result of CXL _OSC negotiation. # # - Emulate CXL DVSEC Range Registers as "decoders": Allow for # first-generation devices that pre-date the definition of the CXL # HDM Decoder Capability to translate the CXL DVSEC Range Registers # into 'struct cxl_decoder' objects. # # - Set timestamp: Per spec, set the device timestamp in case of # hotplug, or if platform-firwmare failed to set it. # # - General fixups: linux-next build issues, non-urgent fixes for # pre-production hardware, unit test fixes, spelling and debug # message improvements" # # * tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (66 commits) # dax/kmem: Fix leak of memory-hotplug resources # cxl/mem: Add kdoc param for event log driver state # cxl/trace: Add serial number to trace points # cxl/trace: Add host output to trace points # cxl/trace: Standardize device information output # cxl/pci: Remove locked check for dvsec_range_allowed() # cxl/hdm: Add emulation when HDM decoders are not committed # cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decoders # cxl/hdm: Emulate HDM decoder from DVSEC range registers # cxl/pci: Refactor cxl_hdm_decode_init() # cxl/port: Export cxl_dvsec_rr_decode() to cxl_port # cxl/pci: Break out range register decoding from cxl_hdm_decode_init() # cxl: add RAS status unmasking for CXL # cxl: remove unnecessary calling of pci_enable_pcie_error_reporting() # dax/hmem: build hmem device support as module if possible # dax: cxl: add CXL_REGION dependency # cxl: avoid returning uninitialized error code # cxl/pmem: Fix nvdimm registration races # cxl/mem: Fix UAPI command comment # cxl/uapi: Tag commands from cxl_query_cmd() # ... # < /opt/cross/kisskb/korg/gcc-8.5.0-nolibc/mips-linux/bin/mips-linux-gcc --version # < /opt/cross/kisskb/korg/gcc-8.5.0-nolibc/mips-linux/bin/mips-linux-ld --version # < git log --format=%s --max-count=1 7c3dc440b1f5c75f45e24430f913e561dc82a419 # < make -s -j 160 ARCH=mips O=/kisskb/build/linus_malta_defconfig_mips-gcc8 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-8.5.0-nolibc/mips-linux/bin/mips-linux- malta_defconfig # < make -s -j 160 ARCH=mips O=/kisskb/build/linus_malta_defconfig_mips-gcc8 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-8.5.0-nolibc/mips-linux/bin/mips-linux- help # make -s -j 160 ARCH=mips O=/kisskb/build/linus_malta_defconfig_mips-gcc8 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-8.5.0-nolibc/mips-linux/bin/mips-linux- olddefconfig # make -s -j 160 ARCH=mips O=/kisskb/build/linus_malta_defconfig_mips-gcc8 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-8.5.0-nolibc/mips-linux/bin/mips-linux- Completed OK # rm -rf /kisskb/build/linus_malta_defconfig_mips-gcc8 # Build took: 0:02:12.000813

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