Buildresult: linus/xtensa-defconfig/xtensa-gcc13 built on Sep 9, 01:34

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Status:	OK
Date/Time:	Sep 9, 01:34
Duration:	0:01:22.939249
Builder:	blade4b
Revision:	Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux (`d1f2d51b711a3b7f1ae1b46701c769c1d580fa7f)`
Target:	linus/xtensa-defconfig/xtensa-gcc13
Branch:	linus
Compiler:	xtensa-gcc13 (xtensa-linux-gcc (GCC) 13.1.0 / GNU ld (GNU Binutils) 2.40)
Config:	defconfig (download)
Log:	Download original No warnings found in log. Full Log # git rev-parse -q --verify d1f2d51b711a3b7f1ae1b46701c769c1d580fa7f^{commit} d1f2d51b711a3b7f1ae1b46701c769c1d580fa7f already have revision, skipping fetch # git checkout -q -f -B kisskb d1f2d51b711a3b7f1ae1b46701c769c1d580fa7f # git clean -qxdf # < git log -1 # commit d1f2d51b711a3b7f1ae1b46701c769c1d580fa7f # Merge: 37d4cc69876f 71c03a8cb213 # Author: Linus Torvalds <torvalds@linux-foundation.org> # Date: Sat Sep 7 11:29:13 2024 -0700 # # Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux # # Pull clk fixes from Stephen Boyd: # "A pile of Qualcomm clk driver fixes with two main themes: the alpha # PLL driver and shared RCGs, and one fix for the Starfive JH7110 SoC. # # - The Alpha PLL clk_ops had multiple problems around setting rates. # # There are a handful of patches here that fix masks and skip # enabling the clk from set_rate() when the PLL is disabled. The PLLs # are crucial to operation of the system as almost all frequencies in # the system are derived from them. # # - Parking shared RCGs at a slow always on clk at registration time # breaks stuff. # # USB host mode can't handle such a slow frequency and the serial # console gets all garbled when the UART clk is handed over to the # kernel. There's a few patches that don't use the shared clk_ops for # the UART clks and another one to skip parking the USB clk at # registration time. # # - The Starfive PLL driver used for the CPU was busted causing cpufreq # to fail because the clk didn't change to a safe parent during # set_rate(). # # The fix is to register a notifier and switch to a safe parent so # the PLL can change rate in a glitch free manner" # # * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: # clk: qcom: gcc-sc8280xp: don't use parking clk_ops for QUPs # clk: starfive: jh7110-sys: Add notifier for PLL0 clock # clk: qcom: gcc-sm8650: Don't use shared clk_ops for QUPs # clk: qcom: gcc-sm8550: Don't park the USB RCG at registration time # clk: qcom: gcc-sm8550: Don't use parking clk_ops for QUPs # clk: qcom: gcc-x1e80100: Don't use parking clk_ops for QUPs # clk: qcom: ipq9574: Update the alpha PLL type for GPLLs # clk: qcom: gcc-x1e80100: Fix USB 0 and 1 PHY GDSC pwrsts flags # clk: qcom: clk-alpha-pll: Update set_rate for Zonda PLL # clk: qcom: clk-alpha-pll: Fix zonda set_rate failure when PLL is disabled # clk: qcom: clk-alpha-pll: Fix the trion pll postdiv set rate API # clk: qcom: clk-alpha-pll: Fix the pll post div mask # < /opt/cross/kisskb/korg/gcc-13.1.0-nolibc/xtensa-linux/bin/xtensa-linux-gcc --version # < /opt/cross/kisskb/korg/gcc-13.1.0-nolibc/xtensa-linux/bin/xtensa-linux-ld --version # < git log --format=%s --max-count=1 d1f2d51b711a3b7f1ae1b46701c769c1d580fa7f # make -s -j 24 ARCH=xtensa O=/kisskb/build/linus_defconfig_xtensa-gcc13 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-13.1.0-nolibc/xtensa-linux/bin/xtensa-linux- defconfig # < make -s -j 24 ARCH=xtensa O=/kisskb/build/linus_defconfig_xtensa-gcc13 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-13.1.0-nolibc/xtensa-linux/bin/xtensa-linux- help # make -s -j 24 ARCH=xtensa O=/kisskb/build/linus_defconfig_xtensa-gcc13 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-13.1.0-nolibc/xtensa-linux/bin/xtensa-linux- olddefconfig # make -s -j 24 ARCH=xtensa O=/kisskb/build/linus_defconfig_xtensa-gcc13 CROSS_COMPILE=/opt/cross/kisskb/korg/gcc-13.1.0-nolibc/xtensa-linux/bin/xtensa-linux- Completed OK # rm -rf /kisskb/build/linus_defconfig_xtensa-gcc13 # Build took: 0:01:22.939249

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